Working remotely from North America or Spain, the full-time Midcore Design Verification Engineer will develop verification strategies, build robust test environments, and debug failures for next-generation high-performance RISC-V CPU cores. Key responsibilities Develop and implement verification strategies and test plans for CPU designs Build and maintain test environments, including architecting test benches and conducting constrained-random testing Collaborate with CPU architects and RTL designers to debug failures and drive issues to resolution Required qualifications 6+ years of experience in design verification for CPUs, SoCs, ASICs, or complex digital designs Strong proficiency in SystemVerilog and UVM, including testbench development and functional coverage Understanding of CPU architecture and microarchitecture concepts such as pipelines and out-of-order execution Experience debugging RTL and simulation failures using common simulation/debug tools Strong programming skills in C/C++ or Python for effective collaboration with design teams
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